Draw a MOD-32 synchronous down counter using J-K flip-flops. [5 marks]

Design a mod-6 (3-bit) counter using only structural code constructs, flip-flops, and Verilog primitive gates. Each student is to implement their design with the configuration of flip-flops and count sequence 7 5 3 2 4 1. The counter should be self-starting after reset from a count value of 7 (seven). All unused states should transition to the reset value. Do Not use any Boolean operators from the Verilog language.Flip-flop order: D, JK, T

74LS93 4 Bit Binary Counter Pinout, Working, Examples and Datasheet