SOLVED: The CSA-based multiplier circuit (scanned from Cavanagh and labeled "A 4-bit carry-save array multiplier") appears to be suboptimal. In particular, two full adders in the first row have 0s as inputs whereas they could also have a0 AND b2 and a1 AND b2 as inputs, respectively. Doing more useful work earlier at no circuit cost should be an improvement (free inputs!). Try redrawing the circuit to maximize the number of full adders with three partial-product bit inputs (replacing a 0, a carr

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