project: implementing the SR_LATCH LAYOUT. Design , simulate and layout an SR latch using NMOS (nchannel MOSFET) and PMOS (p-channel MOSFET) transistors in the 180nm technology using Cadence software.
Abstract: For over 60 years, textbooks on digital logic design have followed a semi-unified way to introduce the concept of digital memory. This method starts from a simple gate-based SR latch and ...
I created cpp_logic_simulation to explore C++ language features and development methodologies that I do not usually use in my C++ work - due to the resource-constrained nature of the typical target ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback