IEEE

A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement

Abstract: This paper describes a Fractional-N Phase Locked Loop (PLL) for multi-phase (=M) clock generation by reducing capacitor area. The M-phase clocks from the Voltage Controlled Ring Oscillator ...
IEEE

Adaptive Fuzzification Methodology for PLL Loop Bandwidth Control: A Framework for Enhanced Locking Precision

Abstract: This paper presents a detailed guided on applying fuzzification techniques to enhance the performance of phase-locked loops (PLLs). PLLs are widely used in high-frequency applications where ...
EDN

Selecting PLLs for ASIC Applications requires tradeoffs

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...
Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
EDN

Optimizing clock synthesis in small cells and heterogeneous networks

Mobile network operators are increasingly turning to small cell base stations to expand coverage, increase capacity and enable network densification in congested, high-traffic urban environments.
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Design-Reuse

Ultra Low Jitter Wide Band LC PLL

The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. Not only must they handle multiple ...
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...
GitHub

KiCad project files and arduino code for an in-expensive and simple phase-locked-loop driver for piezo-electric ultrasonic transducers.

The driver exploits the fact that, at resonance, current and voltage is in phase for a piezoelectric transducer. By locking the driving signal to the current feedback signal, i.e. adjust the driving ...