GitHub

Adder Analysis in VLSI Using Xilinx Vivado

This repository contains the implementation and analysis of various adder architectures in VLSI using Xilinx Vivado design software. The goal of this project is to compare different adder topologies ...
GitHub

vivado.jou

# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023 # Start ...
IEEE

Design Of Majority Carry Save Adder Using Approximation Method For Error-Tolerant Computation

Abstract: The design and computation of energy efficient approximate adder play a crucial role in VLSI. With recent research focusing on approximate computation in digital circuits, there is a growing ...
IEEE

An Efficient Ripple Carry Adder Using Pipelining

Abstract: The Ripple Carry Adder (RPA) is a standard and reliable n-bit adder which uses a combination of Full Adders to sequentially add each bit and give the sum of the n-bit addition as the output.