Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...

Experts at the table: Semiconductor Engineering sat down to discuss why formal verification is becoming more important, with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group ...

Today, project teams build huge verification environments, where verification consumes 40-70% of the resources needed in a typical cycle. Because a verification environment typically contains ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

To some degree, FPGA prototyping has become commonplace in the majority of SoC development programs. This paper is a brief discussion of four aspects of this type of approach. First the forces behind ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Aparna Mohan pioneered a groundbreaking verification methodology for security-critical semiconductor designs that has transformed how the industry approaches security verification, yielding ...