This repository contains a parametric, synthesizable VHDL timer module together with self-checking simulation tests and formal verification. The design is verified using both VUnit (GHDL) and PSL + ...
TIMER_IP is a stopwatch IP Core for embedded systems written in VHDL. The IP component has been developed in VHDL and tested on target device using C. To access the IP component include timer_regs.h ...
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