EDN

“Design and Simulation of an n-bit 3-Number Adder” (Using VHDL) (Nov-Dec 2009)

•The final design for a 16-bit 3 number adder resulted in a worst-case propagation delay (tpd) of 22.017ns with Speculative execution and a group size of 4, an 18.5% improvement from 26.772ns, without ...
Hackaday

Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

Soft cores for FPGAs come in many different flavors, covering a wide range of applications. The Bit-Serial CPU (bcpu) soft core presented by [Richard James Howe] is interesting for taking up just ...