Test patterns play critical roles in physical layer compliance testing by challenging different aspects of a system. Receivers in HSS (high-speed serial) technology must be stable. When the average ...

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...

As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test ...