IEEE

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Abstract: A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks ...
Design-Reuse

Analysis and Summary on Clock Generator Circuits and PLL Design

The demand for analog and mixed-signal-based integrated circuits (ICs) has surged due to the increasing reliance on electronic-based applications across industries. As the world transitions to more ...
IEEE

Analysis of Sub-Sampling PLL False Lock and Lock-in Range Estimation

Abstract: The Sub-sampling PLL (SSPLL) has attracted significant interest from researchers due to its low phase error and high operating frequency. However, the sub ...