An SR latch is a basic memory element in digital electronics that stores binary data using Set and Reset inputs. This tutorial covers the SR latch truth table, the circuit diagram, and the working ...

project: implementing the SR_LATCH LAYOUT. Design , simulate and layout an SR latch using NMOS (nchannel MOSFET) and PMOS (p-channel MOSFET) transistors in the 180nm technology using Cadence software.

Abstract: For over 60 years, textbooks on digital logic design have followed a semi-unified way to introduce the concept of digital memory. This method starts from a simple gate-based SR latch and ...