EDN

Tool claims first transistor-level closed loop PLL verification

SAN FRANCISCO — Claiming an industry first, EDA startup Xpedion Design Systems Inc. introduced a transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter.
EDN

Enhanced PLL circuit design tool can cut design cycles by 80%

Norwood, Mass. — Analog Devices Inc. said that its latest version of its PLL circuit design and evaluation tool helps designers cut design cycles by up to 80 percent. The ADIsimPLL version 2.7 ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...
Design-Reuse

Analysis and Summary on Clock Generator Circuits and PLL Design

The demand for analog and mixed-signal-based integrated circuits (ICs) has surged due to the increasing reliance on electronic-based applications across industries. As the world transitions to more ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
Design-Reuse

Using PLLs to Obtain Carrier Synchronization

An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. Designers typically implement a ...