EDN

Free phase-locked loop (PLL) analysis software

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...
IEEE

A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers

Abstract: The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in ...
Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
IEEE

Adaptive Fuzzification Methodology for PLL Loop Bandwidth Control: A Framework for Enhanced Locking Precision

Abstract: This paper presents a detailed guided on applying fuzzification techniques to enhance the performance of phase-locked loops (PLLs). PLLs are widely used in high-frequency applications where ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Design-Reuse

Is there a "one-size fits all" SOC PLL?

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...