EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 1)

This is Part 1 of a three-part series. As modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher performance than ever before, they’re ...
EDN

PLL design tool offers new modeling data

The ADIsimPLL 2.5 PLL simulation and evaluation tool provides new modeling data to support a broad range of the company's PLL products, such as the ADF4153 and ADF45154 fractional-N PLL synthesizers ...
Design-Reuse

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a ...
Design-Reuse

Low power PLL for short-range mmwave industrial radar

The digitally calibrated charge-pump (CP) PLL can generate high-quality frequency-modulated continuous-wave (FMCW) signals for mmwave radars at low power consumption. The PLL is a critical building ...