Design-Reuse

Efficient logic optimization utilizing complementary behavior of CMOS gates

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...
EurekAlert!

Advances of emerging memristors for in-memory computing applications

The research team led by Researcher Tianyu Wang from the School of Integrated Circuits at Shandong University has systematically reviewed the latest advances in emerging memristors for in-memory ...
Electronics Weekly

Novel logic aims to beat CMOS, on 10 year older fabs

Nottingham-based SFN (Search for the Next) has characterised its novel transistor-based logic, and claims that it matches CMOS performance even when made in older fabs. It would “enable chip designers ...
Semiconductor Engineering

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs

A new technical paper titled “Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing” was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute ...
Design-Reuse

Asynchronous Logic: large CMOS devices without a clock tree

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...
Electronic Design

Automotive ICs Go “Back to the Future” with Minimalist Logic Devices

The history and continued need of small-scale integration ICs for digital-logic functions. How a serial-input/parallel-output shift register can expand I/O pins while ...