Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.

A clock distribution IC does not independently generate a clock signal; as such, phase noise cannot be measured unless an input is applied. The term most commonly used to quantify the quality of a ...

Volumes have been written about jitter, an indication of the complexity associated with timing uncertainty. Actually, timing errors are easy to measure. It is in the assignment of blame that the ...

With the continued quest for ever-higher performance, the unit interval (UI) for a data valid window continues to shrink. At a 1-Gbit/s rate, the UI is 1000 ps, shrinking to 200 ps at 5 Gbits/s and a ...

The three key network specifications for real-time (voice and video) traffic are packet loss, jitter and latency. Whenever I talk to folks about these, they understand the packet loss issue and they ...

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...