IEEE

Improvement of noise tolerance analysis in deep-submicron low voltage dynamic CMOS logic circuits

Abstract: Dynamic CMOS logic circuits are widely employed for improved performance of VLSI chips. However, dynamic CMOS circuits are less resistant to noise than static CMOS circuits. We have given an ...
TechRepublic

Study of Performance of Adiabatic Carry Look Ahead Adder Using Dynamic CMOS Logic

Performance of adiabatic carry look-ahead adder using dynamic CMOS are studied and compared with Adiabatic carry look-ahead adder using Pass Transistor. adiabatic carry look-ahead adder using pass ...
Nature

Wide Fan-In Domino Logic Circuits in CMOS Technology

The rapid evolution of CMOS technology has driven the need for more efficient and high-speed logic circuits, with wide fan-in domino logic circuits emerging as a promising solution. These circuits, ...
Nature

Low Power Design in CMOS and FinFET Logic Circuits

Low power design has become a cornerstone of modern integrated circuit development, driven by energy efficiency demands and the challenges of scaling in nanometre technologies. Innovations in ...
EDN

How to Read Datasheets: Logic ICs (Part 5)

In this column, we consider the evolution of complementary metal-oxide semiconductor (CMOS) technology, which was invented by Frank Wanlass in 1963. In this column, we consider the evolution of ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...