IEEE

Low-power dual-modulus frequency divider by 4/5 up to 13-GHz in 0.13μm CMOS

Abstract: This paper presents a dual-modulus flip-flop-based frequency divider with programmable division ratios by 4/5 designed in a 0.13 μm CMOS technology. The divider is based on a modified CML ...
GitHub

Divide-by-3 Clock Divider with 50% Duty Cycle

A SystemVerilog implementation of a clock frequency divider that divides the input clock by 3 while maintaining a 50% duty cycle output. This project implements a digital clock divider that converts ...
EDN

Integer-N PLL Frequency Synthesizer

The TRF3750 frequency synthesizer is ideal for designing the local oscillator portion of wireless transceivers by providing complete programmability and ultra-low phase noise. The device features a ...
EDN

ADF4106: PLL Frequency Synthesizer block diagram

The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, ...