In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet ...

Over the recent years post-silicon SoC validation has become a major bottleneck in IC design. Due restricted design cycle time and test bench limitations almost all the designs are taped-out with ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...