EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
GitHub

Performance of software decoder on high-resolution HLS playback (frame drops above 480p)

We are implementing dynamic ad insertion on an Android STB device that has a single hardware decoder. Due to certain limitations in our current setup on this device, we need to play live TS content ...
IEEE

HF-LDPC: HLS-friendly QC-LDPC FPGA Decoder with High Throughput and Flexibility

Abstract: LDPC (Low-Density Parity-Check) codes have become a cornerstone of transforming a noise-filled physical channel into a reliable and high-performance data channel in communication and storage ...
IEEE

eLDPC: An Elastic and Scalable LDPC-Decoder with Early Termination by Effectively ...

Abstract: Emerging communication and storage embrace Low-Density Parity-Check (LDPC) codes to fully exploit their physical channels. FPGA (Field-Programmable Gate Array) is widely employed to fast ...