IEEE

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond

Abstract: Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been ...
IEEE

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes

Abstract: This paper presents a VLSI implementation of a Low-Density Parity Check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and ...
TechRepublic

IC Layout Design of Decoder Using Electric VLSI Design System

In this paper, the authors discuss the design of an Integrated Circuit (IC) layout for a decoder. The layout was designed by using an open source software namely electric VLSI design system as the ...
GitHub

Releases: vrindesh/VLSI-Architecture-of-Radix-2-4-8-SISO-Decoder-for-Turbo-Decoding-at-Multiple-Data-rates

You can create a release to package software, along with release notes and links to binary files, for other people to use. Learn more about releases in our docs.
Design-Reuse

Hard IP Core Placement Method in VLSI Physical Design

The hard IP cores, as hard modules, should be pre-placed or placed inside the soft modules as the first step in VLSI physical design. Normally, automatic placer can not obtain good results because ...