GitHub

# CMOS-XNOR-Gate-Design-using-Cadence-Virtuoso

I’m really glad to share that, this is my sixth project on __Cadence Virtuoso__. I am designing here a 2-input CMOS XNOR Gate Design by 4 CMOS NOR Gate, with it's Layout using Cadence Virtuoso. The ...
GitHub

CMOS-NOR-Gate-Schematic-to-GDSII

Introduction of Nor Gate - In CMOS (Complementary Metal-Oxide-Semiconductor) technology, a NOR gate is a fundamental combinational logic gate that outputs logic ‘0’ when any of its inputs are logic ‘1 ...
IEEE

A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate

Abstract: The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of ...
EDN

High-Speed 2-Input NOR Gate

The 74AHC1G02 and 74AHCT1G02 are 2-input NOR gates from the high-speed Si-gate CMOS family. The devices exhibits low power dissipation and high noise immunity for an improved system performance.
EDN

Dual Input NOR Gate

The XC7SET02 is a dual input NOR gate. This high speed CMOS device features symmetrical output impedance, high noise immunity, low power dissipation, balanced propagation delays and ESD protection. It ...
Scientific Research Publishing

Mirmotahari, O. and Berg, Y. (2013) Robust Low-Power CMOS Precharge Logic. Proceedings of the 11th Edition of IEEE Faible Tension Faible Consommation, Paris, June.

ABSTRACT: In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower ...