This project implements an 8-bit Asynchronous FIFO (First-In-First-Out) memory in Verilog. The FIFO supports independent write and read clocks, uses Gray-coded pointers for safe clock domain crossing, ...
This repository contains the RTL design of a 4-bit asynchronous down counter and a fully-functional UVM-based Verification Environment. It demonstrates real-world digital design and verification ...
Abstract: This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock ...
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