HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

東京--(BUSINESS WIRE)--（ビジネスワイヤ） -- Aldec, Inc., システム・FPGA/ASICデザイン向けHDL混合言語シミュレーションと ...

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within ...

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--March 12, 2007--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of ...

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...

Henderson NV, USA – March 24, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology ...

Aldec, Inc., has announced that it has entered into a distribution agreement with Avnet Electronics Marketing Asia. Under the terms of the agreement, Avnet Electronics Marketing will promote and ...