Well known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, Aldec, Inc., has announced the release of Active-HDL 7.1. Active-HDL 7.1 is an FPGA and ASIC design ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...

PLDA’s EZDMA IP and Aldec’s Riviera-PRO and Active-HDL tools enable ease-of-design and robust verification into design environments SAN JOSE, Calif. & HENDERSON, Nev.-- April 28, 2011--PLDA, the ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

QuickLogic Corporation and Aldec, Inc.,announced that QuickLogic is integrating Aldec's Active-HDLTM Lite verification environment into its QuickWorks QuickLogic and Aldec have partnered to provide ...

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--March 12, 2007--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of ...

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within ...

SUNNYVALE, Calif., Feb. 20, 2018 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, display bridge and programmable ...

Aldec, Inc., has announced that it has entered into a distribution agreement with Avnet Electronics Marketing Asia. Under the terms of the agreement, Avnet Electronics Marketing will promote and ...