GitHub

Vineet22dharwadkar/four-bit-adder-subtractor

This project implements a 4-bit Parallel Adder/Subtractor in Verilog using a Ripple Carry Adder (RCA) and logic gates like XOR, AND, and NOT. The design can perform both addition and subtraction based ...
GitHub

parallel_con.xdc

set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {A[0]}] set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {A[1]}] set_property ...
IEEE

Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

Abstract: 32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triple-well 90 nm ...
IEEE

A Comparative Analysis of 8-Bit Parallel Prefix Adder Architectures

Abstract: Digital adders are crucial parts of contemporary computer systems that influence the efficiency of specific arithmetic processes. Parallel prefix adders, like Sparse Kogge, Hancarlson and ...
EDN

Architecting the 4-Bit Chewy Computer

There are many different ways in which we could implement our 4-Bit Chewy Computer — here are a few possibilities for you to peruse and ponder In my previous column on this topic — “Building a 4-Bit ...